In three dimensional packaging, connected integrated circuits are made more compact by vertically stacking two or more dies with a high speed and substantially direct interface. The main reason for vertically stacking dies is better signal performance, i.e. stacked dies are less parasitic as wire length is reduced. Micro ball connections that may be used with vertical die stacks instead of relatively long leads on the periphery of the chips may reduce elapsed time for communication of signals between components, thus increasing speed as wire lengths both between dies in a system and between the circuit and the circuit board may be shortened. In the case of CPU and dynamic random access memory (DRAM) dies, this effect is manifested in higher bandwidth such that there is faster communication between the CPU and DRAM dies. As a secondary reason for vertically stacking dies, vertical die stacks are desirable to reduce the footprint and overall size of the integrated circuits. However, upper or outer vertical dies impede dissipation of heat from lower or inner dies or other components and prevalently increasing processor speeds may generate more heat than previous processors. At the same time, the sizes of dies in general have been reduced, which reduces the surface area available for dissipating heat. One way of operatively interconnecting dies in a die stack is to use through silicon vias (TSV) and silicon-silicon interconnections (SSI).
Accordingly, there is concern with respect to thermal impact and generation of excessive heat in die stacking and in printed board assemblies.
For the foregoing reasons, there is a need for heat to be dissipated from die stacks in packages and other printed board assemblies.